The present invention relates to testing of a wafer used in the fabrication of integrated circuit (IC) dies, and more particularly to testing the wafer in a test fixture using a high pressure fluid.
In the last few decades, the electronics industry has literally transformed the world. Electronic products are used by, or affect the daily lives of, a large segment of the world's population. For example, telephones, television, radios, Personal Computers (PCs), laptop PCs, palmtop PCs, PCs with built-in portable phones, cellular phones, wireless phones, pagers, modems, and video camcorders, are just a few of the electronic products that have been developed in recent years and which have been made smaller and more compact, while providing more and/or enhanced functions than ever before. The integrated circuit (IC) die or IC chip, and the more efficient packaging of the IC die, have played a key role in the success of these products.
There are three distinct stages in the manufacture of an IC die. The first stage is the material preparation. In this stage, the raw materials are mined and purified to meet semiconductor standards. The second stage consists of forming the material into wafers. The diameters of the wafers can vary between 1 and 12 inches. In the third stage, wafer fabrication, the IC dies are formed in and on the wafer. Up to several thousand IC dies can be formed on a wafer but 200 to 300 are more common.
After wafer fabrication is completed, the wafer with the IC dies is mechanically tested to determine if the wafer and IC dies will survive the stresses imposed by final assembly and testing. Also, the tests determine the maximum stress the wafer and IC dies can withstand before the onset of cracking. These tests can act as a guide in the construction of a new IC package.
FIGS. 1a & 1b show the present method of testing. FIG. 1a illustrates a typical three point test setup and FIG. 1b shows a four point test setup. Both of these tests are known in the art. The test piece, which in this case is a silicon wafer 100, is simply supported on two edges by supports 110. These supports prevent the transverse displacement of the edge of the wafer 100 and are made of strong material, such as metal. At the center of the wafer 100, a load 120 (for three point) or a load 130 (for four point) is applied. The load 120 is a single point load and the load 130 uses two points, both of which are applied gradually to the wafer 100. As the load 120 or 130 is applied downwardly, the wafer 100 starts to flex along its length and measurements are made of the load the wafer 100.
The problem associated with the methods of testing shown in FIGS. 1a & 1b is that, as the load 120 or 130 is applied to the wafer 100, there are high stress concentrations at the point where the supports 110 touch the wafer 100 and also at the point where the load 120 or 130 touch the wafer 100. Unfortunately, silicon is a brittle material and is subject to localized cracking or micro-cracking at the point where the test load 120 or 130 is applied and also at the point where the wafer 100 contacts the support members 110. These point load areas generate high local stresses which are the starting point for cracking or micro-cracking. The resultant micro-cracking may influence the test results in uncontrolled ways, thus giving highly variable results. Moreover, the method of testing wafers shown in FIGS. 1a & 1b is not representative of actual loads that an IC die may experience in use because the test only applies point loads on discrete portions of the wafer 100 and does not mechanically test the rest of the wafer 100 or IC dies. In addition, when the wafers are very thin, the weight of the test device (FIGS.s 1a and 1b) may interfere with the test and compromise the results. Removing this inaccuracy by mechanical balancing may be very difficult to achieve, if at all.
Thus, when wafers are currently tested using the methods illustrated in FIGS. 1a & 1b, the contact between the test apparatus and the wafer is an area of high stress concentration and is the starting point of cracking or micro-cracking of the wafer. Disadvantageously, this means that a wafer that might have been good is damaged because of the test fixture and method of testing. As a result, many parts may be disposed of that might otherwise have been good, thus increasing costs.
In current manufacturing practice, the wafers are not mechanically tested for strength.
In view of the above, it is evident that what is needed is an apparatus and method of wafer testing to determine their suitability for use in a high stress package (i.e., flip-chip). The testing can be done prior to die fabrication to determine the base silicone wafers suitability for use in flip-chip or high stress packaging, and post die fabrication to insure the processing was not detrimental to the wafer's original strength. The testing should provide a uniform load distributed over the surface of the wafer, can be used when the IC dies are on the wafer without damaging them, and can be used with many size wafers or components, thereby making the testing more realistic and cost effective.